1. Field of the Invention
The present invention relates to an integrated circuit device, which is synchronized to the phase of a supplied clock, and which comprises a circuit that generates a control clock for achieving a prescribed circuit operation, and to an integrated circuit device, which comprises a control clock generator capable of speeding up phase synchronized operation at reset while curbing power consumption.
2. Description of the Related Art
Dynamic random access memory (DRAM) are operating at increasingly high speeds. Recently, attention has focused on synchronized DRAM (SDRAM), which inputs data and addresses, performs internal operations, and outputs data in synch with an external clock applied from the system side. One of the characteristics of this SDRAM is that it outputs data at a timing that is either in phase synch with an external clock, or which comprises a fixed phase difference with an external clock. Consequently, it is equipped internally with a control clock generator, which generates a control clock for controlling the data output circuit.
For example, this control clock generator comprises a delay-locked loop (DLL) circuit, compares the phase of a dummy output signal from a variable delay circuit with that of a reference clock, and controls the delay time of the variable delay circuit, which delays the reference clock, so that these phases all match up. The applicant, for instance, proposed an example of a circuit, which generates this control clock in Patent Application No. 8-339988 applied for on Dec. 19, 1996. Or, proposed in Patent Application No. 9-68804 applied for on Mar. 21, 1997.
However, in line with increasingly highspeed clock operation, clock phase comparison is performed too frequently, causing an increase of power consumption in the DLL circuit. Accordingly, a configuration that enables reduced power consumption was proposed in the above-described Patent Application No. 9-68804. Although this configuration makes it possible to reduce power consumption, it incurs problems such as slow DLL circuit operation immediately following activation, i.e. powering ON, and the need for a fixed time until phases are ultimately matched up by continuous phase comparison.